VLSI Implementation of low Cost and high Speed convolution Based 1D Discrete Wavelet Transform

This paper presents a new VLSI architecture for a convolution based 1D discrete wavelet transform (DWT) which is intended for high speed signal and image processing. The proposed architecture employing several optimizations that enhance the processing time of the overall hardware design. Firstly we designed the linear phase FIR filter, with pipelined and parallel arithmetic methods, having very less critical path. This filter employs efficiently distributed D-latches and multipliers. Furthermore this filter is used in the proposed DWT architecture. Thus, the new VLSI architecture based on combining of fast FIR filters for reducing the critical path delay and data interleaving technique for lower chip area. We synthesized the final design using Xilinx 9.1i ISE tool. The proposed structure can increase the work frequency at a low cost of additional hardware elements.